Dear All,
My question is very basic : how should I fix this error when compiling ClockDiv_XilinxS6.v on Nexys3 ? how i should change this verilog code ? the answer recored 56113 don't provide the needed code just only the technical/schematic solution.
Error : PhysDesignRules:2502 - Issue with pin connections and/or configuration on block:<uClockDiv/uBUFIO2>:<BUFIO2_BUFIO2>. BUFIO2 has an invalid setting of DIVIDE by 2. This setting is not supported. For more information please see Answer Record 56113.