What does No Cortex-M Device found in JTAG chain mean?
When I try to execute the Blinky program On menu, select Debug -> Start/Stop Debug Session I get a dialog box: JLink - Cortex-M Error No Cortex-M Device found in JTAG chain. Please check the JTAG...
View ArticleIf the mispredict happen, is there a mechanism to abort the instructions(have...
If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)? If there is the mechanism, how does it work? Thanks very much!
View ArticleCortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two...
Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
View ArticleARM Microcontroller Design Contest 2015
Welcome to the forum for the ARM Microcontroller Design Contest! Post your questions regarding the hardware, software or terms of the contest here. Members of the Keil Marketing Team will monitor this...
View ArticleBoard Breakdown: ZYBO Zynq-7000 ***Prize Post***
MAY THE FOURTH BE WITH YOU ALL!!! Happy Nerd-holiday Monday. So I have a few things to share: The first is sorry for the delay there... you will notice the new snazzy "terms and conditions" at the...
View ArticleFIR Filter on Mali 400
Hi everyone. We are trying to use mali 400 GP2 for real time audio processing. Audio data is signed short(16 bit). We implemented FIR filter, but it work very slow for real time processing. We have...
View Article超好用的Atmel开发板免费领啦
各位ARM中文社区的用户： 大家好， 我是版主Ben。今天首先要告诉大家一个极好的消息，我们社区又有免费开发板可以送给大家了。此次我们得到了ARM的好伙伴Atmel 的慷慨支持，我们可以免费为大家提供一款基于Atmel SAM D21 MCU的嵌入式开发板。 开发板视图 首先，请允许我给大家介绍一下这块开发板的主要情况。 这款MCU开发板，主要基于Atmel 的SAM D21 系列ARM®...
View ArticleUsing the whole Cortex-A L2 Cache without external memory
I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory. The CPU boots from an external 4MBytes SPI NOR FLASH chip. It has 512...
View ArticleARMv8-A: Meet the experts – A tour of the new GICv3 architecture -Webinar
Abstract of the Webinar Learn how the GIC, that supports and manages interrupts for processors, will handle next generation designs with larger core counts. The webinar will start with an introduction...
View ArticleRunning openCV 3 with transparent API on Mali GPUs
OpenCV 3 RC1 has been released. It has transparent api to run on CPU or GPU. to make openCV transparent, it uses OpenCL kernels. To run OpenCV on GPU, the GPU should have openCL 1.2 support. My...
View Articlemali T768 上運行opencv ocl face detect example 問題
Hi, 我把opencv OpenCL face detect example 運行在ARM mali T768 後，有以下error message : OpenCL Error Message (Haar face detection): OpenCV Error: Gpu API call (CL_INVALID_EVENT_WAIT_LIST) in void
View ArticleSMMU initialization
Hi, Where i can find step-by-step instruction how to init SMMU PA->IPA translation? (With procedure description) (i checked ARM ® System Memory Management document, but i was not found exact...
View Articledepth component16-32 texture not work on mali t760
i'm doing deferred shading. i use a framebuffer which attach 4 color texture and 1 depth texture as geometrypass. i try to rebuild world position using depth, and use it for lighting. so i need to use...
View ArticleErrors in the Definitive Guide for ARM Cortex-M book series
Embarrassing to say, but just like any other technical documentation, there are a few errors in my books . Over the years I have learn a lot from my mistakes, but it is still impossible to catch all of...
View ArticleSpeech Recognition using Zedboard Zynq 7000 with ARM processor
Does anyone have experience in Speech Recognition ? I am planning to do speech recognition using a Zedboard , I would like to know,how can I achieve it ? and it would be of great help if you can guide...
View ArticleWhat happens in mobile doesn't stay in mobile; how mobile tech quietly blew...
We have been Exploring the world of ARM based Embedded Computing Boards (ECB) here on the ARM Community for 2 months now and its been a real eye opener for me. I've been in the Embedded business for a...
View ArticleIf the mispredict happen, is there a mechanism to abort the instructions(have...
If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)? If there is the mechanism, how does it work? Thanks very much!
View ArticleCortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two...
Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
View ArticleIn Cortex-R4 pipeline, what's the mean by the description"The load-store...
In Cortex-R4 pipeline, what's the mean by the description" The load-store pipeline performs address generation in the issue stage to skew it relative to the other pipelines. This maintains a single...
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