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垫高竞争门槛 飞思卡尔/瑞萨攻64位元车载处理器

来源:新电子   发布者:新电子     车载处理器迈入64位元世代。手机与车机互联发展日益热烧,使得车载处理器规格演进脚步与行动装置应用处理器渐趋一致,除走向异质多核心设计外,亦开始引进64位元架构,包括飞思卡尔(Freescale)与瑞萨电子(Renesas Electronics)皆已宣布投入相关产品研发,期以更高运算效能满足智慧汽车庞大的资讯处理需求。...

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可以介绍一些瑞芯微在广电产品上的应用吗?

我们看到瑞芯微的智能手机应用案例很多。可以介绍一些瑞芯微在广电产品上的应用吗?

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ARM Cortex A8 : Enabling D Cache aborts

I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...

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抱团逐鹿可穿戴市场

各位中文社区的用户,大家好,...

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这可不是上一代的 MCU

嵌入式设计领域在四年之间可以有千变万化;作为回应,ARM 推出了 ARM® Cortex®-M7 处理器,与 2010 年发布 Cortex-M4 相隔也不算远。撰稿人:(特约编辑)carolinehayes ARM 的 Cortex-M4 将 DSP 引入微处理器中;但按照 ARM 嵌入式业务副总裁 Richard York 所述,后来的 Cortex-M7...

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The Mali GPU: An Abstract Machine, Part 3 - The Shader Core

In the first two blogs of this series I introduced the frame-level pipelining [The Mali GPU: An Abstract Machine, Part 1 - Frame Pipelining] and tile based rendering architecture [The Mali GPU: An...

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Rayeager PX2开发板开源代码获取失败注意事项

经常有小伙伴在下载代码的时候遇到下载不能的问题:解决方法:根据wiki描述进行PX2开发板开源代码获取时,遇到Bad owner or permissions on...

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DS-5 error occurs while running HelloWorld

I follow this Getting Started with ARM DS-5 Development Studio | ARM DS-5 Development Studio to run HelloWorld_FVP,error occurs like this:...

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Use of EGL_IMAGE_PRESERVED_KHR in eglCreateImageKHR.

Hi, I am trying to create a sample application where i am trying to use a EGLImage as texture. The EGLImage is created from a native pixmap using eglCreateImageKHR. Most of the open source sample codes...

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『ARM社製品 無料テクニカル相談会』のご案内(2015年04月度)

~...

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Why or how does SysTick interrupt wakeup the processor?

Hello all,I am confusing by SysTick interrupt behavior.Even if SysTick clock was processor clock, the processor woke up from Sleep or DeepSleep mode by SysTick interrupt.My understanding is that the...

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TrustZone - Trusted application development questions

I want to develop a trusted application running on the TEE/TrustZone that is embedded in Android Devices. I contacted a TEE provider and enquired about joining the developer program and getting there...

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The Intelligent Flexible Cloud White Paper

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Lcd 128x32 with lpc111xx

Hello I have a problem with my LPC1114xx because I have to initialize a giant buffer (512) to control the LCD, this is consuming a lot of RAM so I need a way to just print in my display the bitmap that...

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EDA Containers

Linux containers provide a way to build, ship, and run applications such as the EDA tools used in SoC Design and Verification. EDA Containers is a LinkedIn Group to explore and discover the...

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how to set endianness in ARM Cortex-A8

Hi,actually i need to run big endian code but i don't know how to set endian option in cp15 registers could any suggest me how to set EE bit set

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TrustKernel发布基于ARM TrustZone的全系统级安全解决方案

TrustKernel发布基于ARM TrustZone的全系统级安全解决方案T6,兼容目前大多数主流ARM芯片平台,同享使用的便捷与数据的安全。T6是基于ARM TrustZone技术实现的具备可信执行环境(Trusted Execution Environment,...

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updating CPSR in USER UNPRIVILEGED mode

as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is...

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Interview and Question Time with Joseph Yiu

ARM is pleased to announce that Community favourite and Senior Embedded Technology Specialist Joseph Yiu has agreed to take part in a special interview to talk more about our Cortex-M processors. Those...

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Why Cache L1 Counters disable on Streamline

Hello every one,ARM DS-5 (University) streamline to read counter events from Beagle Bone Black board. for some reason i can not get the l1Caches counter to work. Any Advice? Thanks

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