ACTLR[1] question in Cortex-A serias SOC

hi, experts:

I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.

   So, is it only available with Cortex-A9?

   In Cortex-A7 MPCore manual: ACTLR[1] is reserved, so could not disablt outer cache by this method, right?

2. Outer cache question

   In Cortex-A7, L2 Cache controller is also integrated into SCU, so have not outer cache concept, right?

3. In Cortex-A7, SCTLR[2] used to control DCache enable or not.

    So, if wanting to disable DCache, just set SCTLR[2] = 0, not need to disable outer cache(such as L2 Cache) anymore, right?

4. In Cortex-A7, user could not only turn on L1 DCache, and disable L2 Cache, right?

    User must turn L1 DCache and L2 Cache at the same time.

    And if user set SCTLR[2] = 0, then he has disabled L1 DCache and L2 Cache at the same time, right?

best wishes,